This application relates in general to LSI circuit design and is specific to data organization within cache lines.
In a multiprocessor system, problems arise when more than one processor attempts to access a memory location. While multiple processors can access a single memory location, if one of those processors attempts to update the information in the memory location without informing the other processors who also have access to the specific memory location, data mismatches may occur. Multiprocessor systems typically use memory cache which is associated with each processor. These local memory locations are typically called processor cache. Examples of such an architecture are set forth in U.S. Pat. No. 6,049,851 entitled xe2x80x9cMethod and Apparatus for Checking Cache Coherency in a Computer Architecturexe2x80x9d and U.S. Pat. No. 5,737,757 entitled, xe2x80x9cCache Tag System for use with Multiple Processors Including the Most Recently Requested Processor Identificationxe2x80x9d, both patents are assigned to the owner of the present invention, and are incorporated herein by reference in their entirety.
Within the processor cache, the processor may store information as recently accessed. Processor cache is typically separated out into cache lines. A cache line is typically 64, 128, or 256 bytes of data. Therefore, when a processor attempts to access a specific memory location it first searches its cache to determine if it already has a copy of the information stored for that memory location. If the memory location is not currently stored in the processor cache, the processor attempts to obtain a copy of that memory location from main memory. If the memory location is available in the processor cache, the processor will use the cache for its copy. Issues arise when multiple processors attempt to access the same memory location.
Numerous protocols exist which attempt to reduce or eliminate memory contentions between processors. One such protocol is called MESI. MESI stands for Modified, Exclusive, Shared, Invalid and is described in detail in M. Papamarcos and J. Patel xe2x80x9cA Low Overhead Coherent Solution for Multiprocessors with Private Cache Memoriesxe2x80x9d in Proceedings of the 11th International Symposium on Computer Architecture, IEEE, New York (1984), pp. 348-354, incorporated herein by reference. Under the MESI protocol, a cache line is categorized according to its use. A modified cache line indicates that the particular line has been written to by a processor in which case the data has been modified. An exclusive cache line indicates that one specific processor has exclusive access to the line so that it can modify the information contained within that memory location if desired. A shared cache line indicates that more than one processor has access to that memory location. The information in that memory location could also currently be stored in more than one processors"" cache. A shared cache line is considered xe2x80x9cread onlyxe2x80x9d and any processor with access to the memory location can not modify or write to that memory location. An invalid cache line identifies a particular processor""s cache which is invalid i.e., may no longer be current. While MESI is a standard term in the industry, other classifications of nomenclature are frequency employed. Modified cache lines are typically referred to as private dirty. Exclusive cache lines are typically referred to as private cache lines. Private cache lines which have not been modified are typically referred to as private clean cache lines.
If a processor requires access to a specific memory location it will first check its processor cache to determine if the information is available there. If the information is not currently contained within the processor""s cache, the processor will go to main memory to access the information. Before allowing the processor access to a memory location, the cache coherency controller will determine what access to the memory location is available. If a processor desires exclusive or private use of a cache line, it is the function of the cache coherency controller to make sure that no other cache in the system has a valid copy of that line. Only one processor will be allowed exclusive or private access to a memory location at a time. If a cache coherency controller has characterized a specific cache line as read only or shared, potentially every processor or every processor cache in the entire system could have a copy of that line. Difficulties arise, however, if one of the processors needs to update the information within that cache line.
In order for a processor to update or modify information within the specific memory location it must have exclusive access to a memory location. If the memory location is currently categorized as read only, a processor that needs to update or otherwise modify the information must make a request for exclusive access to the memory location. The cache coherency controller then determines which other processors or which other processor cache currently have access to the memory cache line and makes the necessary arrangements for the requesting processor to have exclusive use of the memory cache line.
One method for a processor to obtain the exclusive use of a cache line is for the cache coherency protocol to invalidate other copies of other processor""s access to the memory line cache currently in use. Once other processors access to the memory cache line has been invalidated, the remaining processor has exclusive use of the data and can modify the data as required.
Early attempts at cache coherency included write-through caches that ensured that information was updated simultaneously in memory and in other processor caches. Alternately, if all processors have access to a common memory bus, each processor can listen in or xe2x80x9csnoopxe2x80x9d on the bus for potentially conflicting requests by other processors for exclusive use of the memory location. Once a processor snooped another processor""s request for memory location that the former currently had access to, it could determine that a potential memory conflict may exist. However, snooping requires a common system bus so that every processor could see every other processor""s traffic and make sure the memory they currently have access to was not affected. Snooping also increases overhead, and provides the potential for errors if a message is missed.
Another method of cache coherency is a full directory-based system where rather than sending each transaction to every other agent or other processor in the system a table is maintained which indicates a processor""s access to various cache lines. Regardless of the method used, the job of the cache coherency protocol is to make sure that if there are any caches in a system, especially cache between a processor and a memory, or between system input and output and a memory, and a processor has exclusive use of the line: no other cache has a valid copy of the same exclusive line. Cache coherency controllers can be implemented by processors or by memory.
According to one aspect of the invention, a memory system includes a main memory controller supplying data in response to transactions received by the main memory controller. A plurality of modules each include a cache memory for storing data supplied by the main memory controller. The modules request data from the main memory controller by sending module generated transactions to the main memory controller. A cache tag array includes a cache tag corresponding to at least each data line stored in one of the cache memories of the modules, there being a one-to-one correspondence between the cache tags and the data lines. The data lines together with their associated cache tags are combined and arranged in a plurality of sequential data chunks, the cache tags included in an initial portion of the data chunks (i.e, a first sequence of bits) followed by inclusion of the data lines in a subsequent portion of the data chunks (i.e., the usable bit positions following inclusion of all of the cache tag bits.) By this arrangement, all of the cache tags are transferred between the main memory and the main memory controller prior to transfer of the bits constituting the data lines.
According to a feature of the invention, each of the data chunks includes error correction code (ECC) data for detecting and correcting bit errors of the respective data chunk.
According to another feature of the invention, the cache tag array is coupled to the main memory controller. Further, each of the cache tags specify the module that most recently requested the data line or all of the modules that contain shared copies, preferably independent of whether or not a previous request for the data line has been completed.
According to another feature of the invention, the cache tag array includes information specifying the cache coherency status of each of the data lines that is stored in one of the cache memories.
According to another feature of the invention, the memory controller sends a controller generated transaction requesting one of the data lines to one of the modules when the module receiving the controller generated transaction has a private copy or shared copy of the data line and the data line has been requested by another of the modules. The controller generated transaction identifies the requested data line and the module requesting the data line, the module receiving the controller generated transaction returning the data line or response indicating that no copy of the line exists, and a code identifying the module requesting the data line to the memory controller in a module generated transaction. The main memory controller directs the data line received in one of the module generated transactions to the module identified by the code when the memory controller receives the data line from one of the modules in response to one of the controller generated transactions.
According to another aspect of the invention, a memory system includes a memory controller configured to supply data in response to transactions received by the memory controller. A plurality of modules each having a cache memory for storing data supplied to each of the modules by the memory controller, request data from the memory controller by sending module generated transactions to the memory controller. A memory stores n bit data lines each including (i) p data bits and (ii) q cache tag bits corresponding to the data bits. Each of the data lines is arranged or partitioned into first through r sequential chunks of s bits each wherein n, p, q, r and s are integer values greater than one. An initial portion of the sequential chunks forming one of the data lines including the p cache tag bits and a subsequent portion of the chunks including the n data bits.
According to another feature of the invention, the chunks further includes t bits of respective error correction code.
According to another feature of the invention, the first sequential chunk includes all of the q cache tag bits. Alternatively, if there is insufficient space to include all of the cache bits in the first chunk, then the next sequential chunk or chunks may be used such that the first through ith of the sequential chunks includes the q cache tag bits and the ith (or (i+1)th) through rth of the sequential chunks includes the p data bits.
According to another feature of the invention, the memory controller is responsive to a receipt of the q cache bits to initiate a coherency operation. Preferably, the coherency operation is initiated prior to a receipt of all of the p data bits associated with the q cache bits.
According to another feature of the invention, each of the chunks further includes t bits of error correction code. A. first one of the chunks additionally includes the q cache tag bits and s-(q+t) ones of the p data bits while subsequent ones of the chunks additionally include s-t of the p data bits.
According to another aspect of the invention, a method of maintaining cache memory coherency includes storing n bit data lines each including (i) p data bits and (ii) q cache tag bits corresponding to the data bits. Each of the data lines is arranged in first through r sequential chunks of s bits each wherein n, p, q, r and s are integer values greater than one. An initial portion of the sequential chunks forming one of the data lines includes the p cache tag bits and a subsequent portion of the chunks include the n data bits. In response to a step of sending transactions requesting data, data stored in a memory is supplied as one or more of the data lines, each data line supplied as a sequence of the sequential chunks.
According to another feature of the invention, a step of receiving the first sequential chunk is performed prior to receiving others of the sequential chunks. In response, a coherency operation is initiated prior to a receipt of all r of the sequential chunks.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims.